Silicon Interfaces' 40 Gigabit Ethernet Media Access Controller is highly integrated Gigabit Ethernet MAC solution for Gigabit applications. It simplifies design of Gigabit systems and reduces time-to-market. It is also a companion device for any Network Processor and enables glueless Gigabit Ethernet backbone connectivity.

The 40G EMAC (40 Gigabit Ethernet Media Access Controller) core implements the Ethernet Media Access Control (MAC) protocol according to IEEE 802.3ba specification. The MAC has a standard 40 Gigabit Media Independent Interface (XLGMII) to connect to any PHY interface. The core can be used in various integrated applications. A single channel MAC with PCI controller would provide an ideal solution for inexpensive NIC cards.

The complete modular design of the cores facilitates easy customization to include value added and distinguishing features.

The 40G EMAC implements half duplex functions such as Carrier Extension and Packet Bursting. In full duplex mode, the 40G EMAC implements both symmetrical and asymmetrical flow control via IEEE 802.3x Pause MAC Control frames. Pause frames can be generated according to flow control thresholds within the on-chip receive FIFO.

 

• Product Highlights

 

- 40G EMAC core compliant with IEEE 802.3ba specifications in Full Duplex mode

- Implements a 128-bit XLGMII interface operating at 312.5 MHz

- Generic PCI Host Interface

- Padding of frames on the transmit path if the size of frame is less than 64 bytes

- Frames supported : Normal Frames VLAN Tagged Frames Pause Frames and RUNT Frames

- Programmable frame length providing support for any standard or proprietary frame length (e.g. 9K-Bytes Jumbo  frames)

- Programmable Interframe Spacing (IPG) adjustment which enables precise packet flow control to avoid equipment  overload

 

- Programmable Promiscuous mode to omit MAC destination address checking on receive EMAC

- Supports In-band FCS Enabled Mode

- Implementation of 32-bit CRC polynomial using an efficient pipelined CRC

- Programmable Tx and Rx Packet Length Checking functionality

 

• Product Specifications

 

- Fully synthesizable Register Transfer Level (RTL) Verilog HDL core.

- Functionally verified core. (Verilog)

- Targeted to ASIC (TSMC (0.15, 0.18 and 0.2 micron))

- Standard XLGMII Physical Interface

- Clock Frequency: MHz(TSMC)

 

• Product Options

 

Adaptations:- 32 bit PCI Host Interface (PCI Target)
64 Kbyte (Max) Transmit and 64 Kbyte (Max) Receive External Buffer Memory Interface in place of Internal FIFO,
Powerful statistics database Management Information Database (MIB based on RFC2665) ,
IEEE 802.1q VLAN compliant,
Configurable to handle Jumbo frames up to 9K bytes in length,
Capable of loop-back diagnosis mode,
Supports 802.3ad Link Aggregation and 802.ac Tagging,
Supports 802.3ab, Gigabit Ethernet over copper,
Supports 802.3z, Gigabit Ethernet over Optical Fibers,
Supports IEEE 802.3-2002 specification,
Supports 802.3u 100 Mbits Fast Ethernet

Add-ons :- 16-bit MII (Media Independent Interface)
RMII (6 pin Reduced MII)
PCS Interface physical layer attachment (PMA) for 1000Base-X (i.e. 8b/10b encoding/decoding and SERDES for transmission/reception)
SMII (2 pin Serial MII) Interface

Host Interface: The host Interface allows SI50GE22 to be easily connected to the most 128 bit host processors. The host interface consists of 128-bit data bus.

Physical Interface: The physical (PHY) Interface provides a standard 40 Gigabit media independent interface (XLGMII) to the physical layer

Transmit and Receive FIFO: The Transmit and Receive FIFOs store the transmitted data and the received data.

Control and Status Registers: The Control and Status Registers store vital information desirable for the proper working of the core. It also stores the status of discarded packets while transmission and reception.

Transmitter: The transmitter retrieves data from the transmit memory and constructs Ethernet Frames to be transmitted through the PHY interface.

Receiver: The receiver takes incoming data from the PHY Interface, checks the validity and stores the valid data into the receive memory or stores the status of the received corrupt packet into the CSR.

 

 

40G EMAC Block Representative Schematic: