Silicon Interfaces is a powerhouse of Intellectual Property developed by its team of Engineers. These are owned and copyrighted by Silicon Interfaces and sold as Portfolio of IPs. Silicon Interfaces emerged out of "stealth mode" in the Development Phase effective January 16th, 2002 and unveiled a plethora of 12 IPs and 6+ Verification IP across a broad spectrum.

Silicon IP
Under Silicon Cores Program, we have developed a portfolio of Plug-&-Play IPs spread across various domain such as Interconnect, Data Communications and Networking. Silicon Interfaces' has developed IPs such as PCIe, safeSPI, I3C, USB2.0, 802.11 a/b/g MAC, Gigabit Ethernet MAC, Etc

Verification IP
As a recognized guru in the space of Verification Methodologies, Silicon Interfaces is a company which is the one stop solution for Verification in terms of coverage on Languages, Tools and Methodologies. Silicon Interfaces has the unique position to offer solutions in SystemVerilog based on Accellera^® UVM. Silicon Interfaces has developed Verification Components such as PCIe UVM I2C/I3C UVM, SPI/safeSPI UVM, Etc.

Program Highlights:

The Silicon Cores Program is an IP Development Program and is offered based on three Tier levels, namely Membership, (optional) Product Support Engineering (PSE) and IP Licensing. The Program is targeted to the Networking (wireless and wired), Data Communications and Inter-connect areas, with extensions to Embedded and Storage areas. The program offers a Portfolio of Design IPs and has a program for Roadmap IPs. Memberships are also offered for standalone single IPs, known as Target IPs.

The Design IPs come in a range of plug-&-play hosts, including 8/16/32 bit processor interfaces, AMBA, PCI and more.

Silicon Cores Verification IPs are not part of the Portfolio and Tier 1 Members need to separately license Verification IPs as part of the Tier 3 program and are available for licensing based on perpetual, networked and for worldwide use.

All Silicon Cores Design IPs are targeted to FPGAs from Xilinx, Actel and Altera for synthesis optimizations. Mature IPs have been validated using FPGA target boards as well as siliconized to TSMC, UMC or Chartered .09/.13 CMOS libraries. Certification is available for Design IPs at extra charge.


Tier 1: Membership
This Program is available for Membership based on multi-level Annual Subscription Fees. Membership Levels are based on target industries and prices are based on Usage for Geographical Locations as well as level of Application Engineering (AE) and Product Support Engineering (PSE) support. There are special levels of memberships for Startups, Universities, IP Provider or Resellers and Corporate.

Membership permits the Member rights of internal usage of IP and limited Application Engineer (AE) support. Membership permits Members to guide the Program growth in terms of areas of development as well as Resell the IPs.

The Silicon Cores Program has the following Membership levels based on Annual Subscription
1. Standard - targeted to Universities (per annum), early-stage Start-ups and Post-Evaluation for limited time (3 months) usage
 a.Limited Internal Usage
 b.Only for Site Licensed
2. Premium - targeted to EDA, IP Provider Companies with interest in IP Dev
 a.Limited Internal Usage
 b.Only for Named Site(s) Licensed by Street Addresses, maximum 3 Sites
3. Gold - targeted to Networking, Communications and Storage Companies
 a. Unlimited Internal Usage
 b. All Sites in Country of Membership
4. Platinum - targeted to Foundries, Semiconductor, System House and Networking Majors
 a. Unlimited Internal Usage and Product Development with any one IPs
Tier 2 Support included (some restrictions may apply)
 b. All Sites World-wide

Tier 2:  Membership will assure the Member the option to First Right of Call to Modify and Change the IPs as part of the Product Support Engineering (PSE) as may be required by Member internally or by its customer, at separately agreed and discounted costs; this may pertain to adding/modifying interfaces, low power, faster, lower gate count and other modification required such as re-targeting to ASIC libraries and technologies, etc.

Tier 3:  If external customer were to buy any IP for Member were to use IP for any current design or future SOC, ASICs or FPGAs for Sale, a License Fee (Tier 3) would be payable to Silicon Interfaces. License fees for FPGA are typically 20% of ASIC.

IPs may be classified in three levels

Level 1: Individually priced low per license of usage per design.
(Free with sale of Level 2 and Level 3.)
Example of Level 1 IPs are 8051, 8530, 7990, UART, etc.
Level 2: Individually priced medium per license of usage per design.
Example Level 2 IPs: Gigabit Ethernet, Sonet, Bluetooth and 1394.
Level 3: Individually priced higher per license of usage per design.
Example of Level 3 IPs are: 802.11, Rapid IO, USB2, OTG and Infiniband
The IP Classification may change from time to time.

For more information, please contact siliconcores@siliconinterfaces.com