802.11 a,b and g - WIRELESS LAN (MAC)

Silicon Interfaces’ MAC core for Wireless LAN is compatible with 802.11 a b and g IEEE Standards. It is designed to handle packetized DSSS transmissions; the software implementation supports all Data Rates. The MAC Management or Control Functionality is implemented in hardware.

IEEE 802.11a and IEEE 802.11b and IEEE 802.11g are "High Rate" standard Wireless Local Area Network (WLAN) operating in the 2.4 GHz/5GHz unlicensed Radio Frequency (RF) band and can transmit up to 54 Mbps and 11 Mbps respectively.

SI24WLAN11 is designed to use at higher speeds providing maximum performance with minimum power consumption, without draining the device batteries. It plays active role to save power when there is no frame to transmit or there is no intended frame to receive. This module also indicates about power management status to other modules. It can be used in PCs, Laptop computers, high end PDAs and other devices.

Protocol Firmware is fully compliant with SME (Station Management Entity) and MLME (MAC Sublayer Management Entity) of IEEE 802.11 Standard. It handles complete interrupt handling and event processing for the hardware.

• Applications:

–Wireless Home Networking Devices

–Wireless Audio, Video, Consumer Electronics

–Wireless LAN Adapter

–Wireless LAN STA Terminal, e.g. laptop PC

• Product Highlights

–Fully Compliant with IEEE 802.11a IEEE 802.11b and IEEE 802.11g MAC Layer Functions and Frames.

–Customize to work with all the PHY’ s (IEEE 802.11a, IEEE 802.11b and IEEE 802.11g).

–Supports the role of Station(STA).

–STA operates in both Infrastructures BSS as well as in Independent BSS (IBSS).

–Data rates up to 11 Mbit/sec (802.11b) and 54 Mbit/sec (802.11a and 802.11g).

–Performs CSMA/CA Algorithm to sense the medium.

–AHB Bus Interface.

–Includes WEP based 64-bt Encryption/Decryption Algorithm.

–Supports both Active and Passive Scanning Mode.

–PHY Interface Module handles different Clock Domains between MAC and PHY.

–Optimum Hardware-Software partitioning for reduced gate count as well as lower MIPS requirements.

–Software configurable.

–Synthesizable RTL code for Hardware Component and Csource code for MAC Firmware.

• Product Specifications

–Fully Synthesizable Register Transfer Level (RTL) VHDL.

–Test Bench Environment: VHDL.

–Targeted to Altera Excalibur EP 20K with Embedded 922T ARM Processor at 200 MIPS.

–Clock - 24 MHz for FPGA (Standard: 11 MHz).