PRESS RELEASE
Silicon Interfaces® - authors win the Best Paper Award at the recently concluded DVCon Japan 2023 on June 22nd 2023.
- Silicon Valley, California, 22 June, 2023 9:00 am
In a landmark judgement having great implications and impact in the semiconductor space globally, the Technical Reviewers at the DVCon Japan 2023 at "Kawasaki City Industrial Promotion Hall" in Kanagawa prefecture, JAPAN have awarded Silicon Interfaces authors the BEST PAPER AWARD.
DVCon Japan 2023 (https://www.dvcon-jpn.org/) had selected 3 papers for a presentation.
The topics are
- 3042 - "Integrating L1 & L2 Cache for multi-Core UVM-based extended Low Power Library Package"
- 2489 - "Reducing the simulation life cycle time of Fault Simulations using Artificial Intelligence and Machine Learning techniques on Big Data dataset"
- 7503 - "Addressing Shared IP Instances in a Multi-CPU System Using Fabric Switch A Comprehensive Solution"
Silicon Interfaces received the award for Best Paper for "Reducing the simulation life cycle time of Fault Simulations using Artificial Intelligence and Machine Learning techniques on Big Data dataset".
This is an epoch making watershed day and the recognition of the work and research that Silicon Interfaces has being doing in areas of Low Power integration with UVM Verification Methodologies (UPVM), ISO 26262 based Diagnostic Coverage and Fault Simulation, and PSS based methodologies cross axes portability, said Mrs Heena Bhatia, Chief Business Officer, Silicon Interfaces. Commenting on the effects of these technologies, Prof Purananda Sastry emphasized "the use of AI/ML is imperative for many domains, including ISO 26262 Diagnostic Coverage and Fault Simulation and also to enhance to make our ASICs safer and secure in vast domains in real-world scenarios for industries such as Automotive, Augmented Reality, Drones, Aerospace, Military, and Medical".
About Silicon Interfaces
Silicon Interfaces offers specialized semiconductors and microelectronics services for Low Power Designs, Portable Stimulus Standards (PSS) for Verification, Functional Safety Assurance and Fault Simulation, SystemC TLM, Verilog, SystemVerilog and UVM, EDA tools Product Support/Validation and EDA Infrastructure tools Development in Python/Php/Qt for customers in North America, Europe and Asia Pacific. Please visit www.siliconinterfaces.com
Silicon Interfaces is a powerhouse of Intellectual Property developed by its team of Engineers. These are owned and copyrighted by Silicon Interfaces and sold as Portfolio of IPs. Silicon Interfaces released effective 2002 a plethora of 14 IPs and consequently 6+ Verification IP across a broad spectrum. The Program is targeted to the Wireless and Wired Networking, Data Communications and Inter-connect areas, with extensions to Embedded and Storage areas. The program offers a Portfolio of Design IPs and has a program for Roadmap IPs.
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PRESS RELEASE
Silicon Interfaces® - authors win the Best Paper Award at the recently concluded DVCon Japan 2023 on June 22nd 2023.
- Silicon Valley, California, 22 June, 2023 9:00 am
In a landmark judgement having great implications and impact in the semiconductor space globally, the Technical Reviewers at the DVCon Japan 2023 at "Kawasaki City Industrial Promotion Hall" in Kanagawa prefecture, JAPAN have awarded Silicon Interfaces authors the BEST PAPER AWARD.
DVCon Japan 2023 (https://www.dvcon-jpn.org/) have selected 3 papers for a presentation.
The topics are
- 3042 - "Integrating L1 & L2 Cache for multi-Core UVM-based extended Low Power Library Package"
- 2489 - "Reducing the simulation life cycle time of Fault Simulations using Artificial Intelligence and Machine Learning techniques on Big Data dataset"
- 7503 - "Addressing Shared IP Instances in a Multi-CPU System Using Fabric Switch A Comprehensive Solution"
Silicon Interfaces received the award for Best Paper for "Reducing the simulation life cycle time of Fault Simulations using Artificial Intelligence and Machine Learning techniques on Big Data dataset".
This is an epoch making watershed day and the recognition of the work and research that Silicon Interfaces has being doing in areas of Low Power integration with UVM Verification Methodologies (UPVM), ISO 26262 based Diagnostic Coverage and Fault Simulation, and PSS based methodologies cross axes portability, said Mrs Heena Bhatia, Chief Business Officer, Silicon Interfaces. Commenting on the effects of these technologies, Prof Purananda Sastry emphasized "the use of AI/ML is imperative for many domains, including ISO 26262 Diagnostic Coverage and Fault Simulation and also to enhance to make our ASICs safer and secure in vast domains in real-world scenarios for industries such as Automotive, Augmented Reality, Drones, Aerospace, Military, and Medical".
About Silicon Interfaces
Silicon Interfaces offers specialized semiconductors and microelectronics services for Low Power Designs, Portable Stimulus Standards (PSS) for Verification, Functional Safety Assurance and Fault Simulation, SystemC TLM, Verilog, SystemVerilog and UVM, EDA tools Product Support/Validation and EDA Infrastructure tools Development in Python/Php/Qt for customers in North America, Europe and Asia Pacific. Please visit www.siliconinterfaces.com
Silicon Interfaces is a powerhouse of Intellectual Property developed by its team of Engineers. These are owned and copyrighted by Silicon Interfaces and sold as Portfolio of IPs. Silicon Interfaces released effective 2002 a plethora of 14 IPs and consequently 6+ Verification IP across a broad spectrum. The Program is targeted to the Wireless and Wired Networking, Data Communications and Inter-connect areas, with extensions to Embedded and Storage areas. The program offers a Portfolio of Design IPs and has a program for Roadmap IPs.
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