Silicon Interfaces announces India's No. 1 Semiconductor Services Company - is spreading its wings in Japan, the land of the rising sun

PRESS RELEASE

Silicon Interfaces^® - India's No. 1 Semiconductor Services Company - is spreading its wings in Japan, the land of the rising sun.

Silicon Valley, California, 16 June, 2023 9:00 am

Silicon Interfaces announces its intent to broaden the reach of three core technologies for a) Low Power integration with UVM Verification Methodologies (UPVM), b) ISO 26262 based Diagnostic Coverage and Fault Simulation, and c) PSS based methodologies cross axes portability to the land of the Samurai and the Ninja and builds its pagoda in Japan.

UPVM interleaves functional verification and low power in existing methodologies UVM! Based on these techniques, Silicon Interfaces now has the industry's first integrated Power Verification deployable service platform with near zero ramp-in timelines

The Automotive industry the world over uses Fault Simulation for safety assurance of the cars manufactured, in particularly to address the safety of the hardware components ASICs with the standards ISO 26262 certification based on Safety Critical integrity levels ASIL A, B, C and D to reduce possible hazards caused by the malfunctioning behavior of electrical and electronic (E/E) systems

Portable Stimulus is defined as "An Single Representation of Test Intent that is REUSABLE" by collection of constructs across different levels of integration and different execution platforms. The Accellera Portable Stimulus Standards (PSS) is a Methodology with declarative manner of Domain Specific Language (DSL) with three axes of portability - Vertical, Horizontal and Technique Reuse.

DVCon Japan 2023 (https://www.dvcon-jpn.org/) has selected 3 papers for a presentation. The Conference is scheduled on June 22nd 2023 @ Kawasaki City Industrial Promotion Hall in Tokyo.

The topics are

3042 - "Integrating L1 & L2 Cache for multi-Core UVM-based extended Low Power Library Package"
2489 - "Reducing the simulation life cycle time of Fault Simulations using Artificial Intelligence and Machine Learning techniques on Big Data dataset"
7503 - "Addressing Shared IP Instances in a Multi-CPU System Using Fabric Switch A Comprehensive Solution"

I am confident that our papers and topic, focusing on current industry compelling needs and solutions in the areas of Power Verificationspan^™, Fault Simulation & AI, and Interconnect, will capture your interest and provide valuable insights into the latest advancements in their respective domains, said Mrs Heena Bhatia, Chief Business Officer, Silicon Interfacs.

About Silicon Interfaces

Silicon Interfaces offers specialized semiconductors and microelectronics services for Low Power Designs, Portable Stimulus Standards (PSS) for Verification, Functional Safety Assurance and Fault Simulation, SystemC TLM, Verilog, SystemVerilog and UVM, EDA tools Product Support/Validation and EDA Infrastructure tools Development in Python/Php/Qt for customers in North America, Europe and Asia Pacific. Please visit www.siliconinterfaces.com

Silicon Interfaces is a powerhouse of Intellectual Property developed by its team of Engineers. These are owned and copyrighted by Silicon Interfaces and sold as Portfolio of IPs. Silicon Interfaces released effective 2002 a plethora of 14 IPs and consequently 6+ Verification IP across a broad spectrum. The Program is targeted to the Wireless and Wired Networking, Data Communications and Inter-connect areas, with extensions to Embedded and Storage areas. The program offers a Portfolio of Design IPs and has a program for Roadmap IPs.

<Back to news main