PRESS RELEASE
Silicon Interfaces announces Power Verification™ open source UPVM Low Power Class Library as extension to UVM Package
- Silicon Valley, Calif, 23 May, 2023 9:00 am
Incorporating Power Architecture either is in conjunction with or in sequence to functional verification using different languages, many times with different team members using different tools, and divergent approaches leading to potential errors, almost a fourth dimension to our strategy leveraging the test bench architecture.
Industry seems to be following a parallel path with respect to Methodologies based test bench and Power Architecture, including Unified Power Formats (UPF). Both are fundamental requirements to IP and ASIC verification especially in the power saving mobile world. It would be more efficient to do Methodologies based Functional Verification and Coverage interleaved with Low Power Implementation.
UVM brought in Objects Classes for Verification. UPF unified Power Architecture and Strategies. Silicon Interfaces merged OOPS, UVM and UPF to bring you UPVM.
Why have two sets of engineering for verification and low power? Go green! Low Power helps batteries dissipate slower! Then why waste power with separate Verification and UPF simulation cycles? And burn the midnite oil learning power formats!
With UPVM you interleave functional verification and low power in existing methodologies UVM!
Based on these techniques, Silicon Interfaces now has the industry's first intergrated Power Verification deployable service platform with near zero ramps in timelines. Mrs Heena Bhatia said, Chief Business Officer at Silicon Interfaces stated that with Silicon Interfaces making the UPVM Libraries as Open Source, we are likely to see more participation and more robust ecosystem. The merger of Verification and Low Power is a landmark, game-changing feature which will only help in reducing time to market], at the same time save time and budgets, and ease the burden on project leads to train and deploy engineering talent and avoid re-engineering the wheel, added Prof Sastry, Chief Technical at Silicon Interfaces.
About Silicon Interfaces
Silicon Interfaces offers specialized semiconductors and microelectronics services for complex SoC, ASIC, multi-Core, FPGAs and IPs in areas of Interconnect, Data Communications, Wireless & Wired Networking with special focus on SystemVerilog and UVM, Low Power, Clock Domain Crossing, Portable Stimulus using Portable Stimulus Standards(PSS) and Domain Specific Language (DSL), on lateral techniques Fault Simulation and Emulation for customers in North America, Europe and Asia Pacific.
Silicon Interfaces recommends safeASIC™ technologies for AV/EV, xR, Drones, Aerospace and Military. Silicon Interfaces is demonstrating online, the successful implementation of new technologies. Please visit www.siliconinterfaces.com.
#vlsi #vlsidesign #semiconductors #semiconductor #semiconductorindustry #microelectronics #verification #oops #uvm #upf
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PRESS RELEASE
Silicon Interfaces announces Power Verification™ open source UPVM Low Power Class Library as extension to UVM Package
- Silicon Valley, Calif, 23 May, 2023 9:00 am
Incorporating Power Architecture either is in conjunction with or in sequence to functional verification using different languages, many times with different team members using different tools, and divergent approaches leading to potential errors, almost a fourth dimension to our strategy leveraging the test bench architecture.
Industry seems to be following a parallel path with respect to Methodologies based test bench and Power Architecture, including Unified Power Formats (UPF). Both are fundamental requirements to IP and ASIC verification especially in the power saving mobile world. It would be more efficient to do Methodologies based Functional Verification and Coverage interleaved with Low Power Implementation.
UVM brought in Objects Classes for Verification. UPF unified Power Architecture and Strategies. Silicon Interfaces merged OOPS, UVM and UPF to bring you UPVM.
Why have two sets of engineering for verification and low power? Go green! Low Power helps batteries dissipate slower! Then why waste power with separate Verification and UPF simulation cycles? And burn the midnite oil learning power formats!
With UPVM you interleave functional verification and low power in existing methodologies UVM!
Based on these techniques, Silicon Interfaces now has the industry's first intergrated Power Verification deployable service platform with near zero ramps in timelines. Mrs Heena Bhatia said, Chief Business Officer at Silicon Interfaces stated that with Silicon Interfaces making the UPVM Libraries as Open Source, we are likely to see more participation and more robust ecosystem. The merger of Verification and Low Power is a landmark, game-changing feature which will only help in reducing time to market], at the same time save time and budgets, and ease the burden on project leads to train and deploy engineering talent and avoid re-engineering the wheel, added Prof Sastry, Chief Technical at Silicon Interfaces.
About Silicon Interfaces
Silicon Interfaces offers specialized semiconductors and microelectronics services for complex SoC, ASIC, multi-Core, FPGAs and IPs in areas of Interconnect, Data Communications, Wireless & Wired Networking with special focus on SystemVerilog and UVM, Low Power, Clock Domain Crossing, Portable Stimulus using Portable Stimulus Standards(PSS) and Domain Specific Language (DSL), on lateral techniques Fault Simulation and Emulation for customers in North America, Europe and Asia Pacific.
Silicon Interfaces recommends safeASIC™ technologies for AV/EV, xR, Drones, Aerospace and Military. Silicon Interfaces is demonstrating online, the successful implementation of new technologies. Please visit www.siliconinterfaces.com.
#vlsi #vlsidesign #semiconductors #semiconductor #semiconductorindustry #microelectronics #verification #oops #uvm #upf
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