Gigabit Ethernet MAC System Verilog OVM VIP
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Gigabit Ethernet Media Access Control (MAC) SystemVerilog OVM VIP is fully documented,off-the-shelf component for the Developers of the Gigabit Ethernet MAC.
Gigabit Ethernet Media Access Control (MAC) OVM VIP provides a concise, declarative mechanism to code the specification of sequences of events and activities of Gigabit Ethernet MAC Protocol.
Gigabit Ethernet MAC OVM VIP is developed using the OVM Class Library that provides ovm_sequence, ovm_driver etc. base classes and capabilities, that are used in dynamic simulation of Gigabit Ethernet MAC based design.
The OVM methodology provides the best framework to achieve coverage driven verification. The coverage driven verification combines automatic test generation, self-checking testbenches, and coverage metrics to significantly reduce the time spent verifying a design under test.
• Product Specifications
- The OVM VIP can be adapted to test a standard Gigabit Ethernet MAC device in a Verification environment
- Separate set of tasks provided for Transmit as well as Receive sections in Full-duplex mode
- Extensive checking of the PHY Interface for the MAC
• Product Highlights
- OVM compliant verification Environment.
- Accurately verifies IEEE 802.3 standard Gigabit Ethernet MAC specifications.
- Full programmability and versatility of the VIP allows connection to any standard Gigabit Ethernet MAC device.
- Application of Stimulus to the Generic Microcontroller Interface as well as PHY Interface.
- Provides checking of valid Inter Packet Gap.
- Support for checking of normal as well as VLAN tagged Packets.
- Supports checking of Pause Frames.
- Provides Checkers for Minimum and Maximum payload sizes, for both normal as well as VLAN tagged Packets.
- Checkers to determine validity of Preamble bits along with SFD.
- Separate Configuration file for Parameter definitions.
- Architected with Protocol Checkers, Scoreboard and Monitor.
- Supports scoreboard checking.
- Built in Coverage model implemented for all transaction types.
- Built in Monitors for protocol monitoring and checking.
GEMAC OVM Environment
• GEMAC DUT Description:
The Gigabit Ethernet MAC is connected between the Microcontroller-based Host and Physical Layer. The Microcontroller serves as the Host (Link Layer), which receives and transmits Packets from and to the MAC. The other end of the MAC is connected to the PHY (Physical Layer).
The OVM VIP is built around the DUT as an epicenter.Constructs within monitor the interfaces and provide a detailed log on the transactions that take place to and from the DUT. Thus, just by looking for Successes or Failures within the log output, the function of the Gigabit Ethernet MAC could be easily and effectively validated.
• OVM Environment Description :
GEMAC Virtual Sequencer has collection of virtual sequences to control Host as well as GMII sequences. Sequences are the stimulus data which is fed to the DUT through the Driver. The OVM Class Library provides the ovm_sequence base class. These sequences are derived from the base class. The sequences body tasks are implemented with the specific scenarios to execute the sequences.
The Driver obtains data items from the sequencer for execution. The driver's role is to drive data items to the bus following the interface protocol. The Driver classes are derived from the ovm_driver base class.
Monitor extracts signal information from the bus and translates it into events, structs, and status information. The Monitor functionality includes protocol checking and coverage collection.
A Scoreboard verifies the proper operation of the design at a functional level. It taps the information going in and out of the DUT and determines the DUT response according to the stimulus generated.
Notice: Information in this document is indicative. Product specifications are subject to change without notice. Silicon Interfaces shall not be responsible for direct, indirect or consequential damages that may accrue through typographical errors or otherwise. No license, expressed or implied to any intellectual property rights is granted by this document. Product names mentioned herein may be trademarks and/or registered trademarks of their respective owners. Rights are hereby acknowledged.
Copyright © 2002-2014 Silicon Interfaces Private Limited. All rights reserved.
For more information please contact Silicon Cores at info@siliconinterfaces.com
<Previous product | Next product>
Gigabit Ethernet Media Access Control (MAC) SystemVerilog OVM VIP is fully documented,off-the-shelf component for the Developers of the Gigabit Ethernet MAC.
Gigabit Ethernet Media Access Control (MAC) OVM VIP provides a concise, declarative mechanism to code the specification of sequences of events and activities of Gigabit Ethernet MAC Protocol.
Gigabit Ethernet MAC OVM VIP is developed using the OVM Class Library that provides ovm_sequence, ovm_driver etc. base classes and capabilities, that are used in dynamic simulation of Gigabit Ethernet MAC based design.
The OVM methodology provides the best framework to achieve coverage driven verification. The coverage driven verification combines automatic test generation, self-checking testbenches, and coverage metrics to significantly reduce the time spent verifying a design under test.
• Product Specifications
- The OVM VIP can be adapted to test a standard Gigabit Ethernet MAC device in a Verification environment
- Separate set of tasks provided for Transmit as well as Receive sections in Full-duplex mode
- Extensive checking of the PHY Interface for the MAC
• Product Highlights
- OVM compliant verification Environment.
- Accurately verifies IEEE 802.3 standard Gigabit Ethernet MAC specifications.
- Full programmability and versatility of the VIP allows connection to any standard Gigabit Ethernet MAC device.
- Application of Stimulus to the Generic Microcontroller Interface as well as PHY Interface.
- Provides checking of valid Inter Packet Gap.
- Support for checking of normal as well as VLAN tagged Packets.
- Supports checking of Pause Frames.
- Provides Checkers for Minimum and Maximum payload sizes, for both normal as well as VLAN tagged Packets.
- Checkers to determine validity of Preamble bits along with SFD.
- Separate Configuration file for Parameter definitions.
- Architected with Protocol Checkers, Scoreboard and Monitor.
- Supports scoreboard checking.
- Built in Coverage model implemented for all transaction types.
- Built in Monitors for protocol monitoring and checking.
GEMAC OVM Environment
• GEMAC DUT Description:
The Gigabit Ethernet MAC is connected between the Microcontroller-based Host and Physical Layer. The Microcontroller serves as the Host (Link Layer), which receives and transmits Packets from and to the MAC. The other end of the MAC is connected to the PHY (Physical Layer).
The OVM VIP is built around the DUT as an epicenter.Constructs within monitor the interfaces and provide a detailed log on the transactions that take place to and from the DUT. Thus, just by looking for Successes or Failures within the log output, the function of the Gigabit Ethernet MAC could be easily and effectively validated.
• OVM Environment Description :
GEMAC Virtual Sequencer has collection of virtual sequences to control Host as well as GMII sequences. Sequences are the stimulus data which is fed to the DUT through the Driver. The OVM Class Library provides the ovm_sequence base class. These sequences are derived from the base class. The sequences body tasks are implemented with the specific scenarios to execute the sequences.
The Driver obtains data items from the sequencer for execution. The driver's role is to drive data items to the bus following the interface protocol. The Driver classes are derived from the ovm_driver base class.
Monitor extracts signal information from the bus and translates it into events, structs, and status information. The Monitor functionality includes protocol checking and coverage collection.
A Scoreboard verifies the proper operation of the design at a functional level. It taps the information going in and out of the DUT and determines the DUT response according to the stimulus generated.
Notice: Information in this document is indicative. Product specifications are subject to change without notice. Silicon Interfaces shall not be responsible for direct, indirect or consequential damages that may accrue through typographical errors or otherwise. No license, expressed or implied to any intellectual property rights is granted by this document. Product names mentioned herein may be trademarks and/or registered trademarks of their respective owners. Rights are hereby acknowledged.
Copyright © 2002-2014 Silicon Interfaces Private Limited. All rights reserved.
For more information please contact Silicon Cores at info@siliconinterfaces.com
<Previous product | Next product>