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wUSB^® SI16WUSB10 WIRELESS 2 WIRED DEVICE ADAPTER

wUSB^® SI16WUSB10Wireless2Wired Device Adapter

Silicon Interfaces wUSB device adapter is a highly integrated USB solution for Wireless2Wired USB applications. It simplifies the design of the wUSB systems and reduces the time to market. The SI16WUSB20 is a wUSB functional device adapter core designed as per wUSB 1.0 revision of Wireless USB standards. This core provides 480Mb/s HighSpeed WUSB interface. It autonomously handles the wUSB transactions and data transfers, thus bridging the wUSB interface to an easy read / write parallel microcontroller interface This Wireless USB Function Adapter is a single core solution incorporating Wireless USB connectivity between itself and the Wireless USB host, thereby significantly reducing the time and cost of implementing complex Wireless USB target system designs.

Wireless USB Device Controller is designed to be used in a system to provide Wireless USB connectivity between the device it is being used and the Wireless USB host. This IP is designed based on the Wireless USB specification 1.0 and is backward compatible to the conventional USB 2.0 standard functionality in HighSpeed mode of operation.

The rapidly increasing demands for higher interconnection bandwidth is surpassing the performance capacity of existing interconnect devices. Wireless USB is the new wireless extension to USB that combines the speed of wired technology with the ease-of-use of wireless technology. The wUSB architecture allows up to 127 devices to connect directly to a host. Because there are no wires or ports, there is no longer a need for hubs.

wUSB can also support dual-role devices (DRDs), which in addition to being a wUSB device can function as a host with limited capabilities. For example, a digital camera could act as a device when connected to a computer and as a host when transferring pictures directly to a printer.

It supports transmission and reception of all Frames in the conventional Distributed Coordination Function (DCF) as well as the optional Point Coordination Function (PCF) mode.

• Product Highlights

- Compliant with wUSB specification Rev. 1.0

- Backward Compatible to USB 2.0 standard for HighSpeed transactions

- Mac-PHY Interface signals as per signals defined in ECMA 369 Standard

- Supports WiMedia data rate equivalent to USB HighSpeed data rate of 480 Mbps

- Supports Control, Interrupt, Bulk and Isochronous transfers

- Converts USB2.0 data packets to wireless packets with appropriate MAC headers

- Support for control transfers by Endpoint zero

- Insystem Endpoint FIFO � 1 IN FIFO or EPIN, 1 OUT FIFO or EPOUT and 1 Control FIFO or EPINOUT

- EPIN and/or EPOUT may be considered as Bulk or Isochronous or Interrupt Endpoint

- Endpoint Buffers are integrated 4Kbytes on chip data buffer

- 4 way authentication process; generates device notifications; AES-CCM encryption/decryption

- Wireless USB Device controller Appends and checks FCS sequence

- Supports WiMedia packet processing including error checking

• Product Specifications

- Fully synthesizable Register Transfer Level (RTL) Verilog HDL core.

- Test Bench: Verilog

- Targeted FPGA Xilinx Series 7

- Clock Frequency: 60 MHz for FPGA (Standard: 60 MHz)

• Product Options

  Adaptations: -8-Bit 8051 Microcontroller Interface possible.

  16/32 Bit Host Interface possible. AMBA/AXI possible.

  Add-ons : -SV Test Environment using UVM Methodology

wUSB Block Representative Schematic:

• The wUSB device adapter consists of five main modules: UTMI Interface, Protocol Layer (PL), Endpoint Buffers, Control and Status Registers (CSRs) and Microcontroller Interface.

UTMI Controller:
The intent of UTMI ( USB tranceiver Macrocell Interface) is to accelerate USB2.0 peripheral development. This interface will enable the IP to be able to design, insulated from the high-speed and analog circuitery issues that are associated with the USB2.0 interface.

wUSB Protocol Layer:
PL is the heart of USB device adapter. It is responsible for all USB data I/O and control communications. It includes in itself packet assembler, packet dis-assembler and protocol engine. Packet assembler is responsible for inserting proper PID (packet identifier) and checksums and data field which associates with itself respective CRC generation onto that data, if requested. Packet dis-assembler decodes all incoming packets and forwards the decoded data to the protocol engine and endpoint buffers for further processing. Protocol engine implements standard USB protocol, which includes maintaining the flow of token, data and status paradigm.

Endpoint:
Endpoint buffer is the ultimate source/sink of information. This IP is designed to support 3 endpoints. One is the bi-directional control endpoint used to supply and store configuration related information. Other two endpoints can be configured to support any of the three transfer type�s interrupt, bulk and isochronous by making one IN and other OUT.

Control and Status Registers:
Includes in it information bits which stores the control and status of the current set of operations required by the other blocks.

• Applications :
  - Digital Cameras
  - Digital Camcorders
  - Printers and Scanners
  - External Mass Storage
  - Wireless Hubs
  - Web-cams
  - Portable Audio & Media Players
  - Desktop Speakers
  - Docking Stations and Projectors.

Notice: Information in this document is indicative. Product specifications are subject to change without notice. Silicon Interfaces shall not be responsible for direct, indirect or consequential damages that may accrue through typographical errors or otherwise. No license, expressed or implied to any intellectual property rights is granted by this document. Product names mentioned herein may be trademarks and/or registered trademarks of their respective owners. Rights are hereby acknowledged.

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