VLSI DESIGN : VERIFICATION
VLSI Designs: Verification
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Cadence Incisive Enterprise Simulator 8.1 |
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QuestaSim 6.4 b |
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Synopsys VCS Mx 2009.12 and VERA |
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Specman Elite |
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Magellan |
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Debussy (Novas), Vnavigator Transeda) STM proprietary C Language assembler/compiler toolsets |
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Hardware Accelerator Platforms (AXIS) |
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| • | OVM compliant Gigabit Ethernet MAC System Verilog VIP |
| • | OVM compliant IEEE 1394 (Firewire Link Layer Controller) SystemVerilog VIP. |
| • | VMM based USB 2.0 Function Controller SystemVerilog VIP |
| • | VCS-MX Interface with third party E tool |
| • | ERM/URM Compliant 1394 e/uVC |
| • | USB OVA AIP |
| • | RapidIO VIP |
| • | OpenVera RVM VIP |
| • | Corporate Application Engineering for VCS, IPX and Covermeter for Synopsys |
| • | Verification of Level 3 Mapper SDH/SONET Device |
| • | Verification of SAN Controller ASIC |
| • | Verification of Mainstream – H263/MPEG Video Codec |
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VLSI DESIGN : VERIFICATION
