VLSI Design Services of Silicon Interfaces

Environment	: Linux
Simulation	: Siemens Questa + Visualizer, Synopsys VCS + Verdi
Synthesis	: In-built Synthesis tools
Verification	: VCS with UVM Switch; Questa with UVM switch
PSS/DSL	: Synopsys VCPS
Low Power	: Siemens Questa/PA, Synopsys VCLP
CDC/RDC	: Siemens Questa CDC
Fault Simulation	: SNPS VC-ZOIX, Siemens Austemper SafetyScope Kaleidoscope
FPGA	: AMD Xilinx, Intel Altera, Microsemi Actel, etc.
Emulator	: Synopsys Zebu
Version Control	: Perforce

Environment

: Linux

Entry

: Vim Editor

Simulation

: Siemens Questa + Visualizer, Synopsys VCS + Verdi

Synthesis

: In-built Synthesis tools

Verification

: VCS with UVM Switch; Questa with UVM switch

PSS/DSL

: Synopsys VCPS

Low Power

: Siemens Questa/PA, Synopsys VCLP

CDC/RDC

: Siemens Questa CDC

Fault Simulation

: SNPS VC-ZOIX, Siemens Austemper SafetyScope Kaleidoscope

FPGA

: AMD Xilinx, Intel Altera, Microsemi Actel, etc.

Emulator

: Synopsys Zebu

Version Control

: Perforce

Environment	: Windows
Schematic Entry	: Analog LTspice
Simulation	: LTSspice

Environment

: Windows

Schematic Entry

: Analog LTspice

Simulation

: LTSspice

Networking	: Wireless � 802.11 a+b, Wired - Ethernet MAC
Data Communications	: USB2.0, SPI,SafeSPI, I2C, I3C
Interconnect	: PCIe
Microcontrollers	: 8051

Networking

: Wireless � 802.11 a+b, Wired - Ethernet MAC

Data Communications

: USB2.0, SPI,SafeSPI, I2C, I3C

Interconnect

: PCIe

Microcontrollers

: 8051

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VLSI DESIGN SERVICES

The purpose of the VLSI Design Group is to offer world-class, globally competitive, full-fledged state-of-the-art (a) engineering Design Center for Digital/Analog Design and Verification for the global semiconductors/microelectronics microchip companies as well as (b) infrastructure software development, test EDA tools, customer and product validation services for EDA Companies.

Our VLSI Symphony

Domain Knowledge:

Silicon Interfaces offers Designs Services in the areas of Interconnect, Data Communications and Networking, primarily in the areas of System Verilog/Verilog for Design and Verification of complex SoC, ASIC, multi-Core, FPGAs and IPs. We have a long history of Design Services, now 30+ years in the Silicon Valley and 25+ years in Europe as well as 3+ Years in Japan.

Apart from front-end we also do work on Analog Designs and we offer a complete solution to our Customer.

An interesting aspect of our Design Services is that we undertake work in our state-of-the-art Design Centers based in Mumbai with tools from top leading EDA Companies.

For the AI, Autonomous & Electrical Vehicles, Augmented, Virtual to Experiential Realities (xRs), IoTs, Drones, Aerospace & Military markets, standard Functional Simulation using SV & UVM can only go so far and it may not be far enough to avoid a multi-million dollar re-spin.

Silicon Interfaces recommends going beyond with Portable Stimulus, Low Power design & Clock Domain Crossings validation as well as Fault Simulation with AI/ML and Emulation.

So, if your next design is an IP, ASIC or SOC with a multi-Core implementations, call Silicon Interfaces, especially if the design encompasses Interconnect, Communications and wired and wireless Networking!

Silicon Interfaces, the company which is making it possible to Connect. Communicate. Network.� in the Semiconductor world!

Our Services are leveraged for IP and Development and EDA Product Validation & Support Services.

DESIGN/VERIFICATION:

The activities include Single test Intent Test Bench, Design Entry, Simulation, Debugging, Fault Simulation and Emulation.

The design/verification services include:

Design services for SOC/ASIC/multi-Core/FPGA/IP in SystemVerilog/Verilog by top down methodology
Verification and testing services using SystemVerilog and UVM Methodologies
Portable Stimulus Standards (PSS) for Verification using Domain Specification Language (DSL) enhanced scenarios with parallism for portable stimulus vertifically from IP/Sub-system/SOC & lateral technique reuse for Emulators
ARM C/ASM Programming
Low Power Designs using UPF + IoT
Clock Domain Crossing (CDC) & RDC Design
Functional Safety Assurance and Fault Simulation

Analog Designs

EDA tools Product Support/Validation
EDA Infrastructure tools Development in Python/Php/Qt

Modeling Languages used are:

Verilog & SystemVerilog
Domain Specific Language (DSL)
SystemC

Scripting done in:

Bash and C Shell
Python
TCL

Verification Languages used are:

SystemVerilog

Tools Experience:

Front-End Tools:

Environment	: Linux
Entry	: Vim Editor
Simulation	: Siemens Questa + Visualizer, Synopsys VCS + Verdi
Synthesis	: In-built Synthesis tools
Verification	: VCS with UVM Switch; Questa with UVM switch
PSS/DSL	: Synopsys VCPS
Low Power	: Siemens Questa/PA, Synopsys VCLP
CDC/RDC	: Siemens Questa CDC
Fault Simulation	: SNPS VC-ZOIX, Siemens Austemper SafetyScope Kaleidoscope
FPGA	: AMD Xilinx, Intel Altera, Microsemi Actel, etc.
Emulator	: Synopsys Zebu
Version Control	: Perforce

Analog Tools:

Environment	: Windows
Schematic Entry	: Analog LTspice
Simulation	: LTSspice

Silicon Interfaces has been working in various target domain areas over the years based on specific market needs and has operated in Interconnect, Data Communcations and Networking and other areas.

Currently the focus is on:

Networking	: Wireless � 802.11 a+b, Wired - Ethernet MAC
Data Communications	: USB2.0, SPI,SafeSPI, I2C, I3C
Interconnect	: PCIe
Microcontrollers	: 8051

Methodologies and Standards:

VLSI design methodology
Modeling methodology
VHDL/Verilog modeling standard
Verification methodologies

Verification Methodology:

Develop and model test plan
Develop and model test benches
UVM Methodologies based Test Bench
Portable Standards Specification based Methodlogy Test Bench
Run automated scripts for test plan/test bench
If existing core, capture signals by logic analyzer on existing systems and convert them to test vectors
After prototype is done, run test vectors on prototype running on a daughter board

Project Methodology:

Proposal
Specifications
Project Management - Strategy
Configuration & Change Order Management
Quality Assurance and Risk Management - Strategy
Detail Design
Implementation � Coding & Integration
Verification and Testing
Release

Projects Undertaken:

Onsite:

Gigabit Development Kit ASIC design/ testing for Xaqti Corp, USA
Incorporating Multiple Operating System platform for Sun Workstations undertaken at Sun Microsystems - USA. 1.5 million gates.
Design & test of part of a Multimedia ASIC for Shareware Inc - USA. Subsidiary of Intel & Microsoft
Product support for Synopsys/Cadence - USA.
Design support for Toshiba � USA
Development Wireless LAN Adapter for PDA, Japan
Designing the Advanced Sonet E3/DS3 Receiver/Transmitter (DART) Device
Development of Multi-Codec Pipeline
Design Of Firmware To Activate the Front Panel Logic for Set-top Box of a Cable Modem for HP
Porting MVP (Multi-Media Video Processor) Debugger from Unix to NT.
Parallel debugger manager (PDM) to control debuggers for the processors on the MVP Chip
Design & Testing of the Networking Board for the Gigabit Ethernet Controller for Xaqti Inc - USA.
Verification of Level 3 Mapper SDH/Sonet Device
Development of Automative Embedded Controllers.
Testing VLSI Chips for Various Customers.
Macro Cell Designs for Customers Like Philips - USA.
Design of RF Interface for Barney Toy for Microsoft.
Verification of SAN Controller ASIC
Design and Development of dNTSC Receiver
Verification of Mainstream - H263/MPEG4 Video Codec, UK
Design, testing & synthesis of the receive FIFO of Agni
Corporate Applications Engineer for VCS, IPX and Covermeter for Synopsys

Offshore:

EtherSwitch (100Mb/s) ES100: Specification, Architecture and Validation
Two Port Ethernet-based Switch device.
LAN Analyzer VHDL Model.
Validation of Distributed Networking board.
FPGA (Actel, Xilinx) library development.
VHDL/Verilog libraries for foundries like SMOS, LSI, NCR, etc.
Wireless LAN Adapter.
Cable modem chip for Setup Box
Conversion of Agni and XMAC2 from VHDL to Verilog
Porting of TPC-10 Libraries to Synopsys EDA/Synthesis Tools
eSOC (Extensible System on a Chip) Design and Development

IP Cores Developed by Silicon Interfaces:

RapidIO � Physical Layer Interfaces Core (also VIP, OVA, eVC)
USB2.0 � Function Controller (also OVA, eVC)
InfiniBand � Link Protocol Engine (also eVC)
Bluetooth BaseBand Controller (AMBA Interfaces, also OVA)
Gigabit Ethernet MAC
802.11 a+b � Wireless LAN
SONET � STS-1/3 Framer
7990
1384 � Link Layer Controller
8530 � Serial Communication Controller
UART � Universal Asynchronous Receiver/Transmitter Core
8051 - Microcontroller

Click here to contact Silicon Interfaces for VLSI Design Services.