Skills of Silicon Interfaces

Software

VLSI

Domains Skills Projects R&D

SKILLS

Silicon Interfaces^® teams are skilled in Architecting, Design and Verification of IPs, multi-Cores, ASICs, Chiplets and SOCs. The skills portfolio includes the following:

Modeling Languages used are:

Verilog & SystemVerilog
Domain Specific Language (DSL)
SystemC

Scripting done in:

Bash and C Shell
Python
TCL

Verification Languages used are:

SystemVerilog

Tools Experience:

Front-End Tools:

Environment	: Linux
Entry	: Vim Editor
Simulation	: Siemens Questa + Visualizer, Synopsys VCS + Verdi
Synthesis	: In-built Synthesis tools
Verification	: VCS with UVM Switch; Questa with UVM switch
PSS/DSL	: Synopsys VCPS
Low Power	: Siemens Questa/PA, Synopsys VCLP
CDC/RDC	: Siemens Questa CDC
Fault Simulation	: SNPS VC-ZOIX, Siemens Austemper SafetyScope Kaleidoscope
FPGA	: AMD Xilinx, Intel Altera, Microsemi Actel, etc.
Emulator	: Synopsys Zebu
Version Control	: Perforce

Analog Tools:

Environment	: Windows
Schematic Entry	: Analog LTspice
Simulation	: LTSspice

Software

VLSI

Domains Skills Projects R&D

SKILLS

Verilog & SystemVerilog
Domain Specific Language (DSL)
SystemC

Scripting done in:

Bash and C Shell
Python
TCL

Verification Languages used are:

SystemVerilog

Tools Experience:

Front-End Tools:

Environment	: Linux
Entry	: Vim Editor
Simulation	: Siemens Questa + Visualizer, Synopsys VCS + Verdi
Synthesis	: In-built Synthesis tools
Verification	: VCS with UVM Switch; Questa with UVM switch
PSS/DSL	: Synopsys VCPS
Low Power	: Siemens Questa/PA, Synopsys VCLP
CDC/RDC	: Siemens Questa CDC
Fault Simulation	: SNPS VC-ZOIX, Siemens Austemper SafetyScope Kaleidoscope
FPGA	: AMD Xilinx, Intel Altera, Microsemi Actel, etc.
Emulator	: Synopsys Zebu
Version Control	: Perforce

Analog Tools:

Environment	: Windows
Schematic Entry	: Analog LTspice
Simulation	: LTSspice

Software VLSI

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