VLSI DESIGN : VERIFICATION
FPGA : Test Bench &VDL
- Verilog, VHDL, Vera,E, PSL, SystemVerilog
- Prototypes & Validations
ASIC : High-level and BFM Models
Test Bench & VDL
Protocol, Assertion or Property based
Formal & Hybrid Formal
Post Layout
SOC : System Level Verification
Testing Methodolgies
- OVM, VMM, ERM/URM Compliant Verification Models
