VLSI DESIGN : BACK-END
 |
|
|
Semi Custom: First Encounter
|
|
|
Full Custom
|
|
|
•
|
Cadence Virtuoso |
|
•
|
Tanner Research L-EDIT Pro |
|
DRC, LVS
|
|
|
•
|
Cadence Assura |
|
•
|
Cadence Diva/Dracula |
|
•
|
Tanner Research L-EDIT Pro |
|
•
|
Mentor Calibre |
|
Timing Analysis
|
|
|
•
|
Cadence SignalStorm |
|
Signal Integrity Check
|
|
|
•
|
Cadence CeltIC |
|
•
|
Synopsys Primetime SI (Gate) |
|
•
|
Synopsys Pathmill (Transistor) |
|
Extract
|
|
|
•
|
Cadence Assura /w Parasitic Extraction |
|
Post Layout
|
|
|
•
|
HSPICE |
|
•
|
Orcad PSPICE Simulator |
 |
|
| • | USB2, 1394 and 802.11 a/b/g |
| • | 8 Bit 250 Msamples/Sec DAC |
| • | 100MS/s 8-bit Flash ADC |
| • | 8-bit 250MSPS Pipelined ADC |
| • | 400MHz Clock Synthesizer PLL (0.18u Logic Process) |
| • | High Speed Line Driver |
| • | Automatic Gain Control Circuit |
| • | RFID Tags Layout |
| • | Leaf Cells for Memory Compiler |
VLSI DESIGN : BACK-END
